Technical Standard

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The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface isdivided into independent channels. Each channel is completely independent of one another. Channels arenot necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achievehigh-speed, low power operation. Each channel interface maintains a 128 bit data bus operating at doubledata rate (DDR).

Product Details

Published:

11/01/2018

Number of Pages:

207

File Size:

1 file , 4 MB